As the integrated circuit scales to 32 nm era, the requirements for planarizing an interlayer dielectric are increasingly high. In particular, the success of the mass production of the Intel 45 nm gate-last process promotes greatly the development of advanced technologies of the integrated circuit. Some new challenges and techniques continue to emerge, wherein the planarization of ILD layer for gate-last process is one of the key techniques, which does not exist in the traditional gate-first process.
However, since there is a significant difference in thickness between the surfaces of a polysilicon gate (a dummy gate) and structures on its opposite sides, after multilayer isolating dielectric materials are deposited, protrusions will be formed on a gate-line, causing the overall uniformity of a wafer surface to be poor. Therefore, a good uniformity on the dummy gate will have a significant influence on a subsequent process; otherwise, after the metal gate is filled, significant residuals will exist due to unevenness, resulting in the reliability problem of a device.
In order to improve the uniformity of a wafer, a conventional way is to firstly deposit a layer of SiO2 or further deposit other dielectric layers to improve the electrical isolation performance of a device, and finally a layer of thick spin-on-glass (SOG) dielectric is spin-coated. Next, a heat treatment is performed at a certain temperature, which makes up for the non-uniformity due to the underlying dielectric by means of the excellent backflow performance of SOG. Then, SOG and SiO2 are etched back and removed by means of the plasma etching method, until a planar and uniform surface is created on the dummy gate.
However, such an SOG etch-back method cannot provide a good etching uniformity, and results in that a variation in thickness between different regions on the whole wafer is extremely large, which is due to the fact that the etching rate at the edge is faster than that in the center region, which exacerbates such non-uniformity. The difference in etching rate between different regions results from that a polymer is produced during the etch-back of SOG. Since there is a pressure difference inside the etching chamber, the amount of remaining polymer in different regions determines the value of the etching rate. On the other hand, when etching a composite stack interface, the planarization of thickness is further deteriorated due to difference in etching rate and an etching non-uniformity in different dielectric materials.
In the following, reference is made to FIGS. 1-5 to explain a plasma etch-back technique employed to obtain a planar surface of the ILD or intermetal dielectric (IMD) in a conventional process for manufacturing a semiconductor device.
FIG. 1 shows the basic sequence of a gate-last production process. First, as shown in FIG. 1A, a pad oxide layer 3 is deposited on a substrate 1 with shallow trench isolation (STI) 2, and a dummy gate structure 4 is deposited on the pad oxide layer 3. The dummy gate structure 4 usually comprises a dummy gate of polysilicon or amorphous silicon and isolating spacers of usually nitride on opposite sides of the dummy gate, and may also comprise a capping layer of usually nitride on the dummy gate. Then, as shown in FIG. 1B, ion implant is performed using the dummy gate structure 4 as a mask to form a source/drain structure 5, preferably a lightly doped source/drain (LDD) structure in the substrate 1, and an ILD (denoted as 6 in FIG. 2) of usually oxide is deposited on the overall structure and an SOG is spin-coated, and after a heat treatment reflowing, a planar ILD layer 6 is formed by etching, until the dummy gate structure 4 is exposed. Next, as shown in FIG. 1C, usually the wet etching is adopted to remove the dummy gate structure 4 and the pad oxide layer 3. A gate oxide layer 7 of usually a high-k material such as HfO2, TiO2, Ta2O5, etc. is firstly deposited in a trench left in the ILD layer 6, and a first layer of metal 8, usually TiN, Ti, TaN or Ta or a combination thereof, is then deposited for improving the bonding strength between the materials. Finally, as shown in FIG. 1D, a second layer of metal 9, usually W, Cu, TiAl or Al or a combination thereof, is deposited as a gate metal layer. And polishing is performed, until the ILD layer 6 is exposed. Subsequently, the ILD is etched to form a contact hole structure.
In the step of planarizing the ILD layer 6 as shown in FIG. 1B, a conventional plasma etching process requires two-step etch-back to obtain a planar and uniform surface.
In the first step, an SOG etch-back is performed until reaching the SOG/SiO2 interface. As shown in FIG. 2, obviously, a faster etching rate exists at the edge of the wafer as compared to the center region. When the etching arrives at the SOG/SiO2 interface, the profile of thickness will be similar to a convex shape, as shown in FIG. 3. At the interface, as compared to the thickness in the center region, the edge thickness will be reduced greatly, since the etching already reaches the underlying oxide layer at the interface. The rates of the two layers above and below the interface differ. In particular, when etching the SOG of the upper layer, its etching rate is less than that of SiO2 of the lower layer, which leads to a different etching thickness for a different region and causes the flatness to be reduced greatly.
Next, the second step of etch-back is performed, and a structure as shown in FIG. 4 is formed, of which the thickness is as shown in FIG. 5. In FIG. 5, the horizontal axis represents a distance from the center on the wafer (here taking a 4 inches wafer as an example, its diameter is 10 cm, and thus the whole horizontal axis represents a distance from −5 cm to 5 cm), and the vertical axis represents the thickness of the dielectric material after being etched, which may be measured using an interference metrology tool or an ellipsometer. The etching rate is obtained by measuring the thickness difference of the wafer before and after etching and dividing it by the time for etching. Obviously, the required profiles of thickness and etching rate can be obtained by measuring the thickness values at different positions on the wafer. Furthermore, during etching, since the dielectric materials on opposite sides of the interface differ, a different etching rate will bring about a very large difference in etching thickness. Even if etching back is performed at the same etching rate, the edge effect will tend to be more deteriorated due to the fact that it is difficult to control repeatability and reliability at the interface.
In view of the above, there is a need to provide a new etch-back method for planarizing a semiconductor device.
In U.S. Pat. No. 5,639,345 the planarization performance is improved by using a two-step etching, and in U.S. Pat. No. 5,679,211 a good uniformity is obtained by means of the oxygen in situ treatment. However, a treatment is not performed at the position-near-interface of the stack composite structure, but more just for the SOG layer. Therefore, there is a need to develop a process capable of improving the overall uniformity and obtain a planar surface.
Considering the etching problems encountered in a conventional process and a stack structure, the invention proposes to perform an equal etch rate etch-back at the position-near-interface for a composite stack structure, and obtains a good uniformity performance.